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1 mhz to 1.2 ghz vga with 30 db gain control range ADL5331 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features voltage-controlled amplifier/attenuator operating frequency: 1 mhz to 1.2 ghz optimized for controlling output power high linearity: oip3 47 dbm @ 100 mhz output noise floor: ?149 dbm/hz @ maximum gain input impedance: 50 output impedance: 20 wide gain-control range: 30 db linear-in-db gain control function: 40 mv/db single-supply voltage: 4.75 v to 5.25 v applications transmit and receive power control at rf and if catv distribution functional block diagram inlo vps1 com1 inhi com2 oplo ophi ipbs gain control bias and vref gain com2 rfout com2 vps2 vps2 vps2 com1 vps1 vps2 vps2 com2 com2 opbs nc enbl vps2 rfin 07593-001 input gm stage output (tz) stage continuously variable attenuator ADL5331 figure 1. general description the ADL5331 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 1.2 ghz. the balanced structure of the signal path maximizes signal swing, eliminates common-mode noise and minimizes distortion while it also reduces the risk of spu- rious feed-forward at low gains and high frequencies caused by parasitic coupling. the 50 differential input system converts the applied differential voltage at inhi and inlo to a pair of differential currents with high linearity and good common-mode rejection. the signal currents are then applied to a proprietary voltage- controlled attenuator providing precise definition of the overall gain under the control of the linear-in-db interface. the gain pin accepts a voltage from 0 v at a minimum gain to 1.4 v at a full gain with a 40 mv/db scaling factor over most of the range. the output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. the output stage provides a differential output at ophi and oplo, which must be pulled up to the supply with rf chokes or a center-tapped balun. the ADL5331 consumes 240 ma of current including the out- put pins and operates off a single supply ranging from 4.75 v to 5.25 v. a power-down function is provided by applying a logic low input on the enbl pin. the current consumption in power-down mode is 250 a. the ADL5331 is fabricated on an analog devices, inc., pro- prietary high performance, complementary bipolar ic process. the ADL5331 is available in a 24-lead (4 mm 4 mm), pb-free lfcsp_vq package and is specified for operation from ambient temperatures of ?40c to +85c. an evaluation board is also available.
ADL5331 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation .........................................................................9 applications information .............................................................. 10 basic connections ...................................................................... 10 gain control input .................................................................... 11 cmts transmit application .................................................... 13 interfacing to an iq modulator ................................................ 14 soldering information ............................................................... 14 evaluation board schematic ......................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 5/09revision 0: initial version
ADL5331 rev. 0 | page 3 of 16 specifications v s = 5 v; t a = 25c; m/a-com etc1-1-13 1:1 balun at input and output for single-ended 50 match. table 1. parameter conditions min typ max unit general usable frequency range 0.001 1.2 ghz nominal input impedance 50 nominal output impedance 20 frequency input = 100 mhz gain control span 3 db gain law conformance 30 db minimum gain v gain = 0.1 v ?14 db maximum gain v gain = 1.4 v 17 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.09 db gain control slope 40 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 700 mv output ip3 v gain = 1.4 v, input ?13 dbm per tone, two tone measurement 47 dbm output noise floor v gain = 1.4 v ?149 dbm/hz noise figure v gain = 1.4 v 9 db frequency input = 400 mhz gain control span 3 db gain law conformance 30 db minimum gain v gain = 0.1 v ?15 db maximum gain v gain = 1.4 v 15 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.09 db gain control slope 39.5 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 730 mv output ip3 v gain = 1.4 v, input ?13 dbm per tone, two tone measurement 39 dbm output noise floor 20 mhz carrier offset, v gain = 1.4 v ?150 dbm/hz noise figure v gain = 1.4 v 9 db frequency input = 900 mhz gain control span 3 db gain law conformance 35 db minimum gain v gain = 0.1 v ?18 db maximum gain v gain = 1.4 v 15 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.09 db gain control slope 37 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 800 mv third-order harmonic ?8 dbm outp ut at 900 mhz fundamental ?75 dbc output ip3 v gain = 1.4 v, input ?13 dbm per tone, two tone measurement 32 dbm output noise floor 20 mhz carrier offset, v gain = 1.4 v ?150 dbm/hz noise figure v gain = 1.4 v 9 db gain control input pin gain gain control voltage range 1 0.1 1.4 v incremental input resistance pin gain to pin com1 1 m response time full scale, to within 1 db of final gain 380 ns 3 db gain step, p out to within 1 db of final gain 20 ns
ADL5331 rev. 0 | page 4 of 16 parameter conditions min typ max unit power supplies pin vps1, pin vps2, pin com1, pin com2, pin enbl voltage 4.75 5 5.25 v current, nominal active 240 ma enbl, logic 1, device enabled 2.3 v enbl, logic 0, device disabled 0.8 v current, disabled enbl = logic 0 250 a 1 minimum gain voltage varies with frequency (see , figure , and ). figure 3 4 figure 5
ADL5331 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage vps1 5.5 v supply voltage vps2 5.5 v vps2 to vps1 200 mv rf input power 5 dbm at 50 ophi, oplo 5.5 v enbl vps1 gain vps1 internal power dissipation 1.2 w ja (with pad soldered to board) 56.1c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADL5331 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions 18 17 16 15 1 2 3 24 gain enbl vps2 vps2 vps2 vps2 14 13 vps2 com2 oplo ophi com2 vps2 7 8 9 10 11 com2 com2 com2 opbs ipbs nc 12 4 5 6 vps1 com1 inlo inhi com1 vps1 23 22 21 20 19 ADL5331 top view (not to scale) pin 1 indicator 07593-002 notes 1. nc = no connect. 2. connect the exposed pad to com1 and com2. figure 2. pin configuration table 3. pin function descriptions pin o. neonic description 1, 6 vps1 positive supply. nominally equal to 5 v. 2, 5 com1 common for the input stage. 3, 4 inhi, inlo differential inputs, ac-coupled. 7 nc no connect. 8 ipbs input bias. normally ac-coupled to vps1. a 10 nf capacitor is recommended. 9 opbs output bias. internally compensated, do not connect externally. 10 to 12, 14, 17 com2 common for the output stage. 13, 18 to 22 vps2 positive supply. nominally equal to 5 v. 15, 16 oplo, ophi differential outputs . bias to vpos with rf chokes. 23 enbl device enable. apply lo gic high for normal operation. 24 gain gain control voltage input. nominal range is 0 v to 1.4 v. 25 (epad) ep (epad) exposed paddle.
ADL5331 rev. 0 | page 7 of 16 typical performance characteristics v s = 5 v; t a = 25c; m/a-com etc1-1-13 1:1 balun at input and output for single-ended 50 match. 20 15 10 5 0 ?5 ?10 ?15 ?20 4 3 2 1 0 ?1 ?2 ?3 ?4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 v gain (v) gain (db) error (db) 07593-003 figure 3. gain and gain law conformance vs. v gain over temperature at 100 mhz 20 15 10 5 0 ?5 ?10 ?15 ?20 4 3 2 1 0 ?1 ?2 ?3 ?4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 v gain (v) gain (db) error (db) 07593-004 figure 4. gain and gain law conformance vs. v gain over temperature at 400 mhz 20 15 10 5 0 ?5 ?10 ?15 ?20 4 3 2 1 0 ?1 ?2 ?3 ?4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 v gain (v) gain (db) error (db) 07593-005 figure 5. gain and gain law conformance vs. v gain over temperature at 900 mhz 07593-006 frequency (mhz) 1k 0.1 1 10 100 slope (mv/db) 25 30 15 20 10 5 0 figure 6. gain slope vs. frequency, rfin = ?20 dbm @ 500 mhz, v gain = 1 v 55 50 45 40 35 30 25 20 15 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 v gain (v) oip3 (dbm) 07593-007 figure 7. output ip3 vs. v gain at 100 mhz 45 40 35 30 25 20 15 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 v gain (v) oip3 (dbm) 07593-008 figure 8. output ip3 vs. v gain at 400 mhz
ADL5331 rev. 0 | page 8 of 16 40 35 30 25 20 15 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 v gain (v) oip3 (dbm) 07593-009 figure 9. output ip3 vs. v gain at 900 mhz 07593-010 ch3 200mv ? ch2 500mv m 2.0s 25.0ms/s 40.0ns/pt a ch1 150mv 2 t1: 2.24s t2: 1.2s t: ?1.04s 1/ t: ?961.5khz mean(c1) 1.358v ampl(c1) 3.36v ampl(c2) 900mv figure 10. step response of gain control input 30 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 ?30 50 500 1000 frequency (mhz) gain (db), 50 ? differential source and load 07593-011 v gain = 1.4v v gain = 1.2v v gain = 1.0v v gain = 0.8v v gain = 0.6v v gain = 0.4v v gain = 0.2v v gain = 0v figure 11. gain vs. frequency (differential 50 output load) 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 50 500 1000 frequency (mhz) gain (db), 50 ? differential source and load 07593-012 v gain = 1.4v v gain = 1.2v v gain = 1.0v v gain = 0.8v v gain = 0.6v v gain = 0.4v v gain = 0.2v v gain = 0v figure 12. gain vs. frequency (differential 100 output load) ? 148 ?150 ?152 ?154 ?156 ?158 ?160 0.1 0.3 0.5 0.7 0.9 1.1 1.3 v gain (v) noise (dbm/hz) 07593-028 100mhz 400mhz 900mhz figure 13. output noise spectral density vs. v gain
ADL5331 rev. 0 | page 9 of 16 theory of operation the ADL5331 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 1.2 ghz. this device is intended to serve as an output variable gain amplifier (ovga) for applica- tions where a reasonably constant input level is available and the output level adjusts over a wide range. one aspect of an ovga is that the output metrics, oip3 and op1db, decrease with decreasing gain. the signal path is fully differential throughout the device to provide the usual benefits of differential signaling, including reduced radiation, reduced parasitic feedthrough, and reduced susceptibility to common-mode interference with other circuits. figure 14 provides a simplified schematic of the ADL5331. gain control 07593-016 ophi oplo inhi inlo transimpedance amplifier gm stage figure 14. simplified schematic a controlled input impedance of 50 is achieved through a combination of passive and active (feedback-derived) termination techniques in an input gm stage. note that the inputs of the gm stage are internally biased to a dc level and dc blocking capacitors are generally needed on the inputs to avoid upsetting the operation of the device. the currents from the gm stage are then injected into a balanced ladder attenuator at a deliberately diffused location along the ladder, wherein the location of the centroid of the injection region is dependent on the applied gain control voltage. the steering of the current injection into the ladder is accomplished by proprietary means to achieve linear-in-db gain control and low distortion. linear-in-db gain control is accomplished by the application of a voltage in the range of 0 v dc to 1.4 v dc to the gain control pin, with maximum gain occurring at the highest voltage. the output of the ladder attenuator is passed into a fixed-gain transimpedance amplifier (tza) to provide gain and to buffer the ladder terminating impedance from load variations. the tza uses feedback to improve linearity and to provide controlled 50 differential output impedance. the quiescent current of the output amplifier is adaptive; it is controlled by an output level detector, which biases the output stage for signal levels above a threshold. the outputs of the ADL5331 require external dc bias to the positive supply voltage. this bias is typically supplied through external inductors. the outputs are best taken differentially to avoid any common-mode noise that is present, but, if necessary, can be taken single-ended from either output. the output impedance is 20 differential and can drive a range of impedances from <20 to >75 . back series terminations can be used to pad the output impedance to a desired level. if only a single output is used, it is still necessary to provide a bias to the unused output pin and it is advisable to arrange a reasonably equivalent ac load on the unused output. differential output can be taken via a 1:1 balun into a 50 environment. in virtually all cases, it is necessary to use dc blocking in the output signal path. at high gain settings, the noise floor is set by the input stage, in which case the noise figure (nf) of the device is essentially independent of the gain setting. below a certain gain setting, however, the input stage noise that reaches the output of the attenuator falls below the input-equivalent noise of the output stage. in such a case, the output noise is dominated by the output stage itself; therefore, the overall nf of the device gets worse on a db-per-db basis as the gain is lowered, because the gain is reduced below the critical value. figure 7 through figure 9 provide details of this behavior.
ADL5331 rev. 0 | page 10 of 16 applications information ADL5331 vps1 com1 inhi inlo com1 vps1 nc ipbs opbs com2 com2 com2 vps2 com2 ophi oplo com2 vps2 gain enbl vps2 vps2 vps2 vps2 c7 100pf l1 0.68h l2 0.68h c5 10nf c6 10nf c13 10nf c14 10nf c9 10nf c10 10nf c8 0.1f c1 0.1f c16 100pf c15 0.1f c11 100pf c12 0.1f c2 100pf c3 0.1f c4 100pf vpos rfout v pos v pos rfin v pos v pos gain 07593-017 figure 15. basic connections basic connections figure 15 shows the basic connections for operating the ADL5331. there are two positive supplies, vps1 and vps2, which must be connected to the same potential. connect com1 and com2 (common pins) to a low impedance ground plane. apply a power supply voltage between 4.75 v and 5.25 v to vps1 and vps2. connect decoupling capacitors with 100 pf and 0.1 f power supplies close to each power supply pin. the vps2 pins (pins 13 and pin 18 through pin 22) can share a pair of decoupling capacitors because of their proximity to each other. the outputs of the ADL5331, ophi and oplo, are open collectors that need to be pulled up to the positive supply with 120 nh rf chokes. the ac-coupling capacitors and the rf chokes are the principle limitations for operation at low frequencies. for example, to operate down to 1 mhz, use 0.1 f ac coupling capacitors and 1.5 h rf chokes. note that in some circumstances, the use of substantially larger inductor values results in oscillations. because the differential outputs are biased to the positive supply, ac-coupling capacitors (preferably 100 pf) are needed between the ADL5331 outputs and the next stage in the system. similarly, the inhi and inlo input pins are at bias voltages of about 3.3 v above ground. the nominal input and output impedance looking into each individual rf input/output pin is 25 . consequently, the differential impedance is 50 . to enable the ADL5331, the enbl pin must be pulled high. taking enbl low puts the ADL5331 in sleep mode, reducing current consumption to 250 a at an ambient temperature. the voltage on enbl must be greater than 1.7 v to enable the device. when enabled, the device draws 100 ma at low gain to 215 ma at maximum gain. the ADL5331 is primarily designed for differential signals; however, there are several configurations that can be imple- mented to interface the ADL5331 to single-ended applications. figure 16 and figure 17 show options for differential-to-single- ended interfaces. both configurations use ac-coupling capacitors at the input/output and rf chokes at the output. rfin 10nf 10nf inhi inlo rfout 10nf 10nf ophi oplo ADL5331 rf vga 120nh 120nh +5 v 07593-018 etc1-1-13 etc1-1-13 figure 16. differential operation with balun transformers figure 16 illustrates differential balance at the input and output using a transformer balun. input and output baluns are recom- mended for optimal performance. much of the characterization for the ADL5331 was completed using 1:1 baluns at the input and output for a single-ended 50 match. operation using m/a-com etc1-1-13 transmission line transformer baluns is recommended for a broadband interface; however, narrow- band baluns can be used for applications requiring lower insertion loss over smaller bandwidths.
ADL5331 rev. 0 | page 11 of 16 10nf 10nf inhi inlo rfout rfin 10nf 10nf ophi oplo ADL5331 rf vga 120nh 120nh 5 v etc1-1-13 07593-019 figure 17. single-ended dr ive with balanced output the device can be driven single-ended with similar perfor- mance, as shown in figure 17 . the single-ended input interface can be implemented by driving one of the input terminals and terminating the unused input to ground. to achieve the optimal performance, the output must remain balanced. in the case of figure 17 , a transformer balun is used at the output. gain control input when the vga is enabled, the voltage applied to the gain pin sets the gain. the input impedance of the gain pin is 1 m. the gain control voltage range is between 0.1 v and 1.4 v, which corresponds to a typical gain range between ?15 db and +15 db. the 1 db input compression point remains constant at 3 dbm through the majority of the gain control range, as shown in figure 7 through figure 9 . the output compression point increases decibel for decibel with increasing gain setting. the noise floor is constant up to v gain = 1 v where it begins to rise. the bandwidth on the gain control pin is approximately 3 mhz. figure 10 shows the response time of a pulse on the v gain pin. although the ADL5331 provides accurate gain control, precise regulation of output power can be achieved with an automatic gain control (agc) loop. figure 18 shows the ADL5331 in an agc loop. the addition of a log amp or a trupwr? detector (such as the ad8362 ) allows the agc to have improved temperature stability over a wide output power control range. note that the ADL5331, because of its positive gain slope, in an agc application requires a detector with a negative v out / rf in slope. as an example, the ad8319 in the example in figure 19 has a negative slope. the ad8362 rms detector, however, has a positive slope. extra circuitry is necessary to compensate for this. to operate the ADL5331 in an agc loop, a sample of the output rf must be fed back to the detector (typically using a directional coupler and additional attenuation). a setpoint voltage is applied to the vset input of the detector while vout is connected to the gain pin of the ADL5331. based on the detectors defined linear-in-db relationship between vout and the rfin signal, the detector adjusts the voltage on the gain pin (the detectors vout pin is an error amplifier output) until the level at the rf input corresponds to the applied setpoint voltage. the v gain setting settles to a value that results in the correct balance between the input signal level at the detector and the setpoint voltage. the detectors error amplifier uses clpf, a ground-referenced capacitor pin, to integrate the error signal (in the form of a current). a capacitor must be connected to clpf to set the loop bandwidth and to ensure loop stability. inlo inhi gain oplo ophi directional coupler attenuator vpos comm ADL5331 5 v 5 v clpf vout vset rfin log amp or trupwr detector dac 07593-020 rfin figure 18. ADL5331 in agc loop
ADL5331 rev. 0 | page 12 of 16 inlo inhi gain oplo ophi 10db directional coupler 10db attenuator vpos comm ADL5331 +5 v +5v +5 v comm vout vpos vset inhi inlo clpf ad8319 log amp dac rfin signal rfout signal 390 ? 1k? setpoint voltage 220pf 1nf 1nf 120nh 120nh 10nf 10nf 07593-021 10nf 10nf figure 19. ad8319 operating in controller mode to provide automatic gain control functionality in combination with the ADL5331 figure 19 shows the basic connections for operating the ad8319 log detector in an automatic gain control (agc) loop with the ADL5331 . the gain of the ADL5331 is controlled by the output pin of the ad8319 . the voltage, v out , has a range of 0 v to near v pos . to avoid overdrive recovery issues, the ad8319 output voltage can be scaled down using a resistive divider to interface with the 0.1 v to 1.4 v gain control range of the ADL5331. a coupler/attenuation of 21 db is used to match the desired maximum output power from the vga to the top end of the linear operating range of the ad8319 (approximately ?5 dbm at 900 mhz). figure 20 shows the transfer function of the output power vs. the v set voltage over temperature for a 100 mhz sine wave with an input power of ?1.5 dbm. note that the power control of the ad8319 has a negative sense. decreasing v set , which corresponds to demanding a higher signal from the ADL5331, increases gain. this agc loop is capable of controlling signals of ~30 db, which is the gain range limitation on the ADL5331. across the top 25 db range of output power, the linear conformance error is within 0.5 db over temperature. 20 15 10 5 3.00 2.25 1.50 ?0.75 ?1.50 ?2.25 ?3.00 0 0.75 0 ?5 ?10 ?15 ?20 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 v set (v) output power (dbm) error from straight line at 25c (db) +85c +25c ?40c 07593-022 figure 20. ADL5331 output power vs. ad8319 setpoint voltage, p in = 0 dbm at 100 mhz
ADL5331 rev. 0 | page 13 of 16 for the agc loop to remain in equilibrium, the ad8319 must track the envelope of the output signal of the ADL5331 and provide the necessary voltage levels to the gain control input of the ADL5331. figure 21 shows an oscilloscope of the agc loop depicted in figure 19 . a 100 mhz sine wave with 50% am modulation is applied to the ADL5331. the output signal from the vga is a constant envelope sine wave with amplitude corres- ponding to a setpoint voltage at the ad8319 of 1.3 v. the gain control response of the ad8319 to the changing input envelope is also shown in figure 21 . 07593-023 ad8319 output ch1 250mv ? ch2 200mv ch3 250mv ? m2.00ms a ch4 1.80v 1 2 3 t 0.00000s t t ADL5331 output am modulated input figure 21. oscilloscope showing an am modulated input signal and the response from the ad8319 figure 22 shows the response of the agc rf output to a pulse on vset. as vset decreases from 1.5 v to 0.4 v, the agc loop responds with an rf burst. in this configuration, the input signal to the ADL5331 is a 1 ghz sine wave at a power level of ?15 dbm. 07593-024 ch3 200mv ? ch2 500mv m 4.0s 12.5ms/s 80.0ns/pt a ch1 150mv 2 t1: 4.48s t2: 2.4s t: ?2.08s 1/ t: ?480.8khz mean(c1) 440.3mv curs2 pos 2.4s curs1 pos 4.48s ampl(c1) 3.36v ampl(c2) 900mv figure 22. oscilloscope showing theresponse time of the agc loop response time and the amount of signal integration are con- trolled by clpf. this functionality is analogous to the feedback capacitor around an integrating amplifier. while it is possible to use large capacitors for clpf, in most applications, values under 1 nf provide sufficient filtering. more information on the use of ad8319 in an agc application can be found in the ad8319 data sheet. cmts transmit application interfacing to ad9789 because of its broadband operating range, the ADL5331 vga can also be used in direct-launch cable modem termination systems (cmts) applications in the 50 mhz to 860 mhz cable band. the ADL5331 makes an excellent choice as a post-dac vga in a cmts application when used with the analog devices ad9789 wideband dac. the ad9789 also contains digital signal processing specifically designed to process docsis type cmts signals. a typical ad9789-to-ADL5331 interface is shown in figure 23 . 0 7593-025 16ma 16ma 50? 55? 20? ad9789 dac 25 ? 70 ? vga 5v series termination figure 23. block diagram of ad9789 interface to ADL5331 in a docsis type application
ADL5331 rev. 0 | page 14 of 16 interfacing to an iq modulator the basic connections for interfacing the ADL5331 with the adl5385 are shown in figure 24 . the adl5385 is an rf quadrature modulator with an output frequency range of 50 mhz to 2.2 ghz. it offers excellent phase accuracy and amplitude balance, enabling high performance direct rf modulation for communication systems. the output of the adl5385 is designed to drive 50 loads and easily interfaces with the ADL5331. the input to the ADL5331 can be driven single-ended, as shown in figure 17 . similar configurations are possible with the adl537x family of quadrature modulators. these modulators can provide outputs from 500 mhz to 4 ghz. soldering information on the underside of the chip scale package, there is an exposed compressed paddle. this paddle is internally connected to the chips ground. solder the paddle to the low impedance ground plane on the printed circuit board to ensure specified electrical performance and to provide thermal relief. it is also recom- mended that the ground planes on all layers under the paddle be stitched together with vias to reduce thermal impedance. 10nf 10nf inhi inlo rf output 10nf 10nf ophi comm vpos oplo 5 v 5v etc1-1-13 lo ibbp ibbn qbbp qbbn comm vpos 5v gain control 100pf 100pf differential i/q baseband inputs dac dac vout adl5385 iq mod 68h 68h ADL5331 rf vga 07593-030 figure 24. adl5385 quadrature modulator and ADL5331 interface
ADL5331 rev. 0 | page 15 of 16 evaluation board schematic agnda ophia vps2a vps2a agnda agnda agnda agnda v ps1a inhia vps1a agnda vps2a agnda agnda sw1a agnda agnda ipbsa opbsa vs2a 78 9101112 25 13 14 15 16 17 18 1 2 3 6 4 5 19 20 2122 23 24 vs1a c13a 100pf c10a 100pf c7a 100pf agnda c8a 0.1f c9a 0.1f c16a 10nf c11a c12a r12a 0 ? rsa 0 ? r16a 0 ? r3a 1k? r1a 0 ? r17a 10k ? r2a 0 ? agnda c1a 100pf agnda c2 0.1f agnda c17a 1000pf r6a 0 ? r4a 0 ? r9a 0 ? vs1a c15a 10nf l1a 0.68h l2a 0.68h t2a c14a 0.1f c3a 0.1f c4a 100pf 1 34 25 c11a 10nf c12a 10nf t1a 1 34 2 5 gaina enbla vps1a gna enb_a 3 1 2 v ps1 a vps1a testloop blue testloop red testloop black v ps2 a vps2a gnd a agnda enbla vps1a vps2a gaina ipbsa opbsa vrefa agnda r14a 0 ? p1a 1 p1a 2 p1a 3 p1a 4 p1a 5 p1a 6 p1a 7 p1a 8 07593-026 vps1 com1 inhi inlo com1 vps1 ipbs nc opbs com2 com2 com2 vps2 vs2a com2 ophi oplo com2 vps2 epad enbl gain vps2 vps2 vps2 vps2 z1a ADL5331 figure 25. ADL5331 single-ended input/output evaluation board
ADL5331 rev. 0 | page 16 of 16 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bo ttomview) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 080808-a figure 26. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity ADL5331acpz-r7 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq] cp-24-2 1,500 ADL5331acpz-wp 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq] cp-24-2 250 ADL5331-evalz 1 ADL5331 evaluation board 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07593-0-5/09(0)

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